1. Field of the Invention
The present invention relates to a method of fabricating a dynamic random access memory (DRAM), and more particularly to a method of fabricating a lower electrode of a DRAM capacitor.
2. Description of the Related Art
A dynamic random access memory cell, normally called a memory cell, includes a transistor and a capacitor. The capacitor is used to store a bit of data in a memory device. Data storage for DRAM selectively charges or discharges each capacitor in the capacitor array on a semiconductor substrate. When the thickness and dielectric constant of capacitor dielectric layer are both fixed for a capacitor with a fixed operative voltage, the capacitance of the capacitor is decided by the surface area of the capacitor electrode.
The size of a DRAM cell is gradually reduced as the integration of integrated circuits is continuously increased. It is well known by people skilled in the art that the capacitance of the capacitor is decreased since its size is reduced. The decreased capacitance easily causes soft errors by .alpha. rays, which results in a data storage failure in the memory cells. Therefore, a capacitor structure with high integration and capacitance is required, thereby keeping a desired capacitance under the circumstances in which the size of the capacitor is reduced to make possible a DRAM with high capacitance and good performance.
A method in the prior art of increasing the surface area of capacitor electrode is to increase the height of the capacitor. However, increasing the height of the capacitor relatively increases the aspect radio of the contact, and thus increases the difficulty of contact etching.